Embodiments of the present embodiments relate to a programmable semiconductor controlled rectifier (SCR) for electrostatic discharge (ESD) protection and having programmable switching and holding voltages.
Referring to FIG. 1A, there is a current-voltage diagram of a semiconductor controlled rectifier (SCR) of the prior art. FIG. 1B is a simplified diagram of the SCR showing the PNPN impurity layers and intervening junctions J1-J3. Here and in the following discussion it should be understood that a semiconductor controlled rectifier may also be called a silicon controlled rectifier or a thyristor as described by S. M. Sze, “Semiconductor Devices Physics and Technology” 148-156 (John Wiley & Sons 1985). In general, a silicon controlled rectifier is a special case of a semiconductor controlled rectifier that is specifically formed on a silicon substrate. The current-voltage diagram shows a reverse blocking region 100 where junctions J1 and J3 are reverse biased, but junction J2 is forward biased. By way of contrast, junctions J1 and J3 are forward biased, but junction J2 is reverse biased in the forward blocking region 102. At switching voltage Vsw 104, the SCR switches from the forward blocking region to a minimum holding voltage (Vh) and holding current (Ih) region 106. Each point along line 108 is a relatively higher holding current and holding voltage, and the slope of line 108 represents the on resistance of the SCR. In this mode all three junctions J1-J3 are forward biased and the minimum holding voltage across the SCR may be as low as a single diode drop or approximately 0.7 V. In holding regions 106 and 108, therefore, the SCR functions as a near ideal switch with very little power dissipation due to the low holding voltage and holding current.
SCRs have been used for primary protection against electrostatic discharge (ESD) for several years. Rountree first disclosed a lateral SCR for ESD protection (FIG. 2A) in U.S. Pat. No. 5,012,317, issued Apr. 30, 1991, having a priority date of at least Apr. 14, 1986. The SCR was also described in detail by Rountree et al. in “A Process Tolerant Input Protection Circuit for Advanced CMOS Processes” (EOS/ESD Symposium Proceedings, pp. 201-205, 1988). The SCR was connected between input terminal 200 and ground terminal 202. The SCR provided a significant improvement in failure threshold over existing ESD protection circuits. However, it required a relatively high switching voltage (Vsw) to induce avalanche conduction at the N− and P− 204 linear junction J2.
Rountree subsequently disclosed a low voltage SCR for ESD protection (FIG. 2B) in U.S. Pat. No. 4,939,616, issued Jul. 3, 1990, having a priority date of at least Nov. 1, 1988. The low voltage SCR maintained the substantially improved failure threshold of the original lateral SCR. The low voltage SCR also substantially reduced the switching voltage (Vsw) required for avalanche conduction by forming an abrupt junction J2 between the N+ and P− regions.
Polgreen et al. later disclosed an even lower voltage SCR for ESD protection (FIG. 2C) in U.S. Pat. No. 5,465,189, issued Nov. 7, 1995, having a priority date of at least Mar. 5, 1990. This SCR modified the SCR of U.S. Pat. No. 4,939,616 by adding a grounded gate n-channel transistor 206 between junctions J2 and J3. The increased electric field at the gate-to-drain overlap region near junction J2 induced avalanche conduction at the SCR switching voltage, which was substantially lower than previously disclosed lateral SCRs. (col. 4, lines 30-35). At the same time, the SCR raised several reliability concerns, because the SCR functioned as a grounded gate n-channel transistor between the forward blocking region 102 and the switching voltage 104. For some processes and test conditions, therefore, it is possible that the gate oxide at the gate-to-drain overlap region near junction J2 may rupture before the SCR turns on.
A common feature of the SCRs of FIGS. 2A through 2C is that the switching voltage of each is determined by the avalanche threshold of p-n junction J2. Other circuits have included secondary protection circuits, such as an isolation resistor and grounded gate n-channel transistor, to achieve a relatively lower switching voltage. This, however, requires the avalanche threshold of the n-channel transistor plus the voltage drop across the isolation resistor to forward bias junction J1. Others have used series-connected diodes to forward bias junction J1. This, however, increases leakage current in normal circuit operation. Still others have used junction-isolated base regions to reduce SCR switching (Vsw) and holding (Vh) voltages. This, however, may require a triple well process or other special isolation techniques. Moreover, any application of a low impedance control signal before the integrated circuit is adequately powered up may cause the SCR to latch and destroy itself. Thus, all these circuits of the prior art offer some advantages albeit with corresponding disadvantages. These and other problems are resolved by the following embodiments of the present invention as will become apparent in the following discussion.